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january 2007 hyb18t512400bf hyb18t512800bf hyb18t512160bf 512-mbit double-data-rate-two sdram ddr2 sdram rohs compliant products internet data sheet rev. 1.05
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hyb18t512xxxbf?[2.5?5] 512-mbit double-data-rate-two sdram qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 03292006-ybym-wg0z hyb18t512400bf, hyb18t512800bf revision history: 2007-01, rev. 1.05 page subjects (major changes since last revision) all qimonda update all adapted internet edition previous version: 2005-11, rev. 1.04 32 added al 5 and 6 and rtt 50 ohms
internet data sheet 3 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 1overview this chapter gives an overview of the 512-mbit double -data-rate-two sdram product family and describes its main characteristics. 1.1 features the 512-mbit double-data-rate-two sdra m offers the following key features: ? 1.8 v 0.1 v power supply 1.8 v 0.1 v (sstl_18) compatible i/o ? dram organizations with 4, 8 and 16 data in/outputs ? double data rate architec ture: two data transfers per clock cycle four internal banks for concurrent operation ? programmable cas latency: 3, 4, 5 and 6 ? programmable burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differential data strobes (dqs and dqs ) are transmitted / rece ived with data. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on-die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-ref resh and power saving power-down modes ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c ? programmable self refresh rate via emrs2 setting ? programmable partial array refresh via emrs2 settings ? dcc enabling via emrs2 setting ? full and reduced strength data-output drivers ? 1kb page size for 4 & 8, 2kb page size for 16 ? packages: p-tfbga-60 for 4 & 8 components p- tfbga-84 for 16 components ? rohs compliant products 1) ? all speed grades faster th an ddr400 comply with ddr400 timing specifications when run at a clock rate of 200 mhz. a list of the performance tables for the various speeds can be found below ? table 1 ?performance for ddr2?800? on page 4 ? table 2 ?performance for ddr2?667? on page 4 ? table 3 ?performance for ddr2?533c? on page 4 ? table 4 ?performance for ddr2?400b? on page 5 1) rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2 002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmiu m, hexavalent chromium, po lybrominated biphenyls and polybrominated biphenyl ethers.
internet data sheet 4 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 1 performanc e for ddr2?800 product type speed code ?2.5f ?2.5 unit speed grade ddr2?800d 5?5?5 ddr2?800e 6?6?6 ? max. clock frequency @cl6 f ck6 400 400 mhz @cl5 f ck5 400 333 mhz @cl4 f ck4 266 266 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 12.5 15 ns min. row precharge time t rp 12.5 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 57.5 60 ns table 2 performanc e for ddr2?667 product type speed code ?3 ?3s unit speed grade ddr2?667c 4?4?4 ddr2?667d 5?5?5 ? max. clock frequency @cl5 f ck5 333 333 mhz @cl4 f ck4 333 266 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 12 15 ns min. row precharge time t rp 12 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 57 60 ns table 3 performanc e for ddr2?533c product type speed code ?3.7 unit speed grade ddr2?533c 4?4?4 ? max. clock frequency @cl5 f ck5 266 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns
internet data sheet 5 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 1.2 description the 512-mb ddr2 dram is a high-speed double- data-rate-two cmos dram device containing 536,870,912 bits and internally configured as a quad- bank dram. the 512-mb device is organized as either 32 mbit 4i/o 4 banks, 16 mbit 8i/o 4 banks or 8mbit 16 i/o 4 banks chip. these devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. see table 1 to table 4 for performance figures. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. off-chip driver (ocd ) impedance adjustment 5. on-die termination (odt) function. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 16-bit address bus for 4 and 8 organized components and a 15-bit address bus for 16 components is used to convey row, column and bank address information in a ras -cas multiplexing style. the ddr2 device operates with a 1.8 v 0.1 v power supply. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in pg-tfbga package. table 4 performanc e for ddr2?400b product type speed code ?5 units speed grade ddr2?400b 3?3?3 ? max. clock frequency @cl5 f ck5 200 mhz @cl4 f ck4 200 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 40 ns min. row cycle time t rc 55 ns
internet data sheet 6 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram note: for product nomenclature see chapter 9 of this data sheet table 5 ordering information for rohs compliant products product type org. speed cas-rcd-rp latencies 1)2)3) 1) cas: column address strobe 2) rcd: row column delay 3) rp: row precharge clock (mhz) cas-rcd-rp latencies clock (mhz) package hyb18t512160bf-25f 16 ddr2-800d 5-5-5 400 4-4-4 266 pg-tfbga-84-8 hyb18t512800bf-25f 8 ddr2-800d 5-5-5 400 4-4 -4 266 pg-tfbga-60-24 hyb18t512400bf-25f 4 ddr2-800d 5-5-5 400 4-4 -4 266 pg-tfbga-60-24 hyb18t512160bf-2.5 16 ddr2-800e 6-6-6 400 5-5-5 333 pg-tfbga-84-8 hyb18t512800bf-2.5 8 ddr2-800e 6-6-6 400 5-5 -5 333 pg-tfbga-60-24 hyb18t512400bf-2.5 4 ddr2-800e 6-6-6 400 5-5 -5 333 pg-tfbga-60-24 hyb18t512160bf-3 16 ddr2-667c 4-4-4 333 3-3-3 200 pg-tfbga-84-8 hyb18t512400bf-3 4 ddr2-667c 4-4-4 333 3-3 -3 200 pg-tfbga-60-24 hyb18t512800bf-3 8 ddr2-667c 4-4-4 333 3-3 -3 200 pg-tfbga-60-24 hyb18t512160bf-3s 16 ddr2-667d 5-5-5 333 4-4-4 266 pg-tfbga-84-8 hyb18t512400bf-3s 4 ddr2-667d 5-5-5 333 4-4 -4 266 pg-tfbga-60-24 hyb18t512800bf-3s 8 ddr2-667d 5-5-5 333 4-4 -4 266 pg-tfbga-60-24 hyb18t512160bf-3.7 16 ddr2-533c 4-4-4 266 3-3-3 200 pg-tfbga-84-8 hyb18t512400bf-3.7 4 ddr2-533c 4-4-4 266 3-3 -3 200 pg-tfbga-60-24 hyb18t512800bf-3.7 8 ddr2-533c 4-4-4 266 3-3 -3 200 pg-tfbga-60-24 hyb18t512160bf-5 16 ddr2-400b 3-3-3 200 ? ? pg-tfbga-84-8 hyb18t512400bf-5 4 ddr2-400b 3-3-3 200 ? ? pg-tfbga-60-24 hyb18t512800bf-5 8 ddr2-400b 3-3-3 200 ? ? pg-tfbga-60-24
internet data sheet 7 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 2 pin configuration 2.1 pin configuration the pin configuration of a ddr2 sd ram is listed by function in table 6 . the abbreviations used in the pin# and buffer type columns are explained in table 7 and table 8 respectively. the pin numbering for the fbga package is depicted in figure 1 for 4, figure 2 for 8 and figure 3 for 16 . table 6 pin configuration of ddr2 sdram ball#/pin# name pin type buffer type function clock signals 4/ 8 organizations e8 ck i sstl clock signal ck, complementary clock signal ck f8 ck isstl f2 cke i sstl clock enable clock signals 16 organization j8 ck i sstl clock signal ck, complementary clock signal ck note: see functional description in x4/x8 organization k8 ck isstl k2 cke i sstl clock enable note: see functional description in x4/x8 organization control signals 4/ 8 organizations f7 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) g7 cas isstl f3 we isstl g8 cs isstl chip select control signals 16 organization k7 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas isstl k3 we isstl l8 cs isstl chip select address signals 4/ 8 organizations g2 ba0 i sstl bank address bus 1:0 g3 ba1 i sstl
internet data sheet 8 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram h8 a0 i sstl address signal 12:0, address signal 10/autoprecharge h3 a1 i sstl h7 a2 i sstl j2 a3 i sstl j8 a4 i sstl j3 a5 i sstl j7 a6 i sstl k2 a7 i sstl k8 a8 i sstl k3 a9 i sstl h2 a10 i sstl ap i sstl k7 a11 i sstl l2 a12 i sstl l8 a13 i sstl address signal 13 note: x4/x8 512 mbit components nc ? ? note: and x16 512 mbit components address signals 16 organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl l1 nc ? ? m8 a0 i sstl address signal 12:0, address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl data signals 4 organizations c8 dq0 i/o sstl data signal 3:0 c2 dq1 i/o sstl d7 dq2 i/o sstl d3 dq3 i/o sstl table 6 pin configuration of ddr2 sdram ball#/pin# name pin type buffer type function
internet data sheet 9 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram data signals 8 organization c8 dq0 i/o sstl data signal 7:0 c2 dq1 i/o sstl d7 dq2 i/o sstl d3 dq3 i/o sstl d1 dq4 i/o sstl d9 dq5 i/o sstl b1 dq6 i/o sstl b9 dq7 i/o sstl data signals 16 organization g8 dq0 i/o sstl data signal 15:0 g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe 4 / 8 organisations b7 dqs i/o sstl data strobe a8 dqs i/o sstl data strobe 8 organisations b3 rdqs o sstl read data strobe a2 rdqs osstl data strobe 16 organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl data mask 4 / 8 organizations b3 dm i sstl data mask data mask 16 organization table 6 pin configuration of ddr2 sdram ball#/pin# name pin type buffer type function
internet data sheet 10 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram b3 udm i sstl data mask upper/lower byte f3 ldm i sstl power supplies 4/ 8 / 16 organizations a9,c1,c3,c7, c9 v ddq pwr ? i/o driver power supply a1 v dd pwr ? power supply a7,b2,b8,d2, d8 v ssq pwr ? i/o driver power supply a3,e3 v ss pwr ? power supply power supplies 4/ 8 organizations e2 v ref ai ? i/o reference voltage e1 v ddl pwr ? power supply e9,h9,l1 v dd pwr ? power supply e7 v ssdl pwr ? power supply j1,k9 v ss pwr ? power supply power supplies 16 organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply e7, f2, f8, h2, h8 v ssq pwr ? i/o driver power supply j7 v ssdl pwr ? power supply j3,n1,p9 v ss pwr ? power supply not connected 4 organizations a2, b1, b9, d1, d9, g1, l3,l7, l8 nc nc ? not connected not connected 8 organization g1, l3,l7, l8 nc nc ? not connected not connected 16 organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other pins 4/ 8 organizations f9 odt i sstl on-die termina tion control other pins 16 organization k9 odt i sstl on-die termina tion control table 6 pin configuration of ddr2 sdram ball#/pin# name pin type buffer type function
internet data sheet 11 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 7 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 8 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 op erational states, active low and tristate, and allows multiple devices to share as a wire-or.
internet data sheet 12 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram figure 1 pin configuration for 4 components, pg-tfbga-60-24 notes 1. v ddl and v ssdl are power and ground for the dll.they are isolated on the device from v dd , v ddq , v ss , and v ssq 2. ball position l8 is a13 for 512-mbit and is not connected on 256-mbit - 0 0 4 #3 "! .# .# 6 2%& ! ! 0 .# ! ! ! ! ! ! .# $1 $- 3 3 6 ! ! ! $1 $13 6 33$, 6 331 6 $$1 6 331 ! .# ! 6 $$1 .# $1 .# ! " # $ & ' ( * % , + 6 $$ 3 3 1 6 6 $$1 $1 6 $$1 3 3 1 6 6 $$, 3 3 6 7 % #+% #+ "! .# 3 3 6 6 $$ $ 1 3 #!3 6 $$1 6 331 #+ 6 $$ 2!3 /$4 6 $$ ! 6 . # ! 33
internet data sheet 13 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram figure 2 pin configuration for 8 components, pg-tfbga-60-24 notes 1. rdqs / rdqs are enabled by emrs(1) command. 2. if rdqs / rdqs is enabled, the dm function is disabled 3. when enabled, rdqs & rdqs are used as strobe signals during reads. 4. v ddl and v ssdl are power and ground for the dll. v ddl is connected to v dd on the device. v dd , v ddq , v ssdl , v ss , and v ssq are isolated on the device. 5. ball position l8 is a13 for 512-mbit and is not connected on 256-mbit. -004 #3 $ 1 $ 1 "! 6 . # 2%& ! ! 0 2$13 ! ! ! ! ! ! .# $1 $- 2$13 3 3 6 ! ! ! $1 $13 6 33$, 6 331 6 $$1 6 331 ! .# ! 6 $$1 $1 $1 $1 ! " # $ & ' ( * % , + 6 $$ 3 3 1 6 6 $$1 $1 6 $$1 3 3 1 6 6 $$, 3 3 6 7 % #+% #+ "! .# 3 3 6 6 $$ $ 1 3 #!3 6 $$1 6 331 #+ 6 $$ 2!3 /$4 6 $$ ! 6 . # ! 33
internet data sheet 14 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram figure 3 pin configuration for 16 components, pg-tfbga-84-8 notes 1. udqs/udqs is data strobe for dq[15:8], ldqs/ldqs is data strobe for dq[7:0] 2. ldm is the data mask signal for dq[7:0], udm is the data mask signal for dq[15:8] 3. v ddl and v ssdl are power and ground for the dll. v ddl is connected to v dd on the device. v dd , v ddq , v ssdl , v ss , and v ssq are isolated on the device. - 0 0 4 6 $ $ . # ! 6 3 3 1 .# 6 3 3 # + % # + 6 3 3 5 $ - $ 1 6 $ $ 1 $ 1 $ 1 6 3 3 6 $ $ , ! 6 3 3 1 $ 1 , $ 1 3 2 ! 3 6 $ $ ! " # $ & ' ( * % , - + . $ 1 6 $ $ " ! " ! ! ! 0 ! 6 3 3 6 $ $ 1 $ 1 $ 1 6 3 3 $ , ! ! ! $1 . # 6 $ $ . # 0 2 ! ! ! ! . # 6 3 3 $ 1 6 $ $ 1 6 3 3 1 $ 1 , $ - 6 $ $ 1 6 $ $ 1 $1 6 3 3 1 $1 6 2 % & 7 % . # ! ! 5$ 1 3 5 $ 1 3 $ 1 6 $ $ 1 6 $ $ 1 $ 1 6 3 3 1 $ 1 6 3 3 1 6 $ $ 1 , $ 1 3 6 3 3 1 6 $ $ 1 $ 1 6 $ $ 1 6 3 3 1 # + 6 $ $ / $ 4 # ! 3 # 3 6 3 3 1 6 3 3 1
internet data sheet 15 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 2.2 512 mbit ddr2 addressing table 9 512-mbit ddr2 addressing configuration 128mb x 4 1) 1) refered to as ?org? 64mb x 8 32mb x 16 note bank address ba[1:0] ba[1:0] ba[1:0] ? number of banks 4 4 4 ? auto-precharge a10 / ap a10 / ap a10 / ap ? row address a[13:0] a[13:0] a[12:0] ? column address a11, a[9:0] a[9:0] a[9:0] ? number of column address bits 11 10 10 2) 2) refered to as ?colbits? number of i/os 4 8 16 ? page size [bytes] 1024 (1k) 1024 (1k) 2048(2k) 3) 3) pagesize = 2 colbits org/8 [bytes]
internet data sheet 16 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 3 functional description table 10 mode register definition (ba[2:0] = 000b) field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 , bank address ba1 15 bank address [1] 0 b ba1 , bank address ba0 14 bank address [0] 0 b ba0 , bank address a13 13 address bus[13] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a13 , address bit 13 pd 12 w active power-down mode select 0 b pd , fast exit 1 b pd , slow exit wr [11:9] w write recovery 2) note: all other bit combinations are illegal. 001 b wr , 2 010 b wr , 3 011 b wr , 4 100 b wr , 5 101 b wr , 6 dll 8 w dll reset 0 b dll , no 1 b dll , yes tm 7 w test mode 0 b tm , normal mode 1 b tm , vendor specific test mode cl [6:4] w cas latency note: all other bit combinations are illegal. 010 b cl , 2 011 b cl , 3 100 b cl , 4 101 b cl , 5 110 b cl , 6 - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 0 $ 7 2 " , r e g a d d r w w w w w w $ , , 4 - # , " 4 w
internet data sheet 17 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram bt 3 w burst type 0 b bt , sequential 1 b bt , interleaved bl [2:0] w burst length note: all other bit combinations are illegal. 010 b bl , 4 011 b bl , 8 1) w = write only register bits 2) number of clock cycles for write reco very during auto-precharge. wr in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr [cycles] t wr (ns) / t ck (ns). the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing wr min is determined by t ck.max and wr max is determined by t ck.min . table 10 mode register definition (ba[2:0] = 000b) field bits type 1) description table 11 extended mode register definition (ba[2:0] = 001b) field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 , bank address ba1 15 bank address [1] 0 b ba1 , bank address ba0 14 bank address [0] 0 b ba0 , bank address - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 1 o f f 2 $ 1 3 $ 1 3 / # $ 0 r o g r a m 2 t t ! , 2 t t $ ) # $ , , r e g a d d r w w w w w w w w
internet data sheet 18 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram a13 13 w address bus[13] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a13 , address bit 13 qoff 12 output disable 0 b qoff , output buffers enabled 1 b qoff , output buffers disabled rdqs 11 read data strobe output (rdqs, rdqs) 0 b rdqs , disable 1 b rdqs , enable dqs 10 complement data strobe (dqs output) 0 b dqs , enable 1 b dqs , disable ocd program [9:7] off-chip driver calibration program 000 b ocd , ocd calibration mode exit, maintain setting 001 b ocd , drive (1) 010 b ocd , drive (0) 100 b ocd , adjust mode 111 b ocd , ocd calibration default al [5:3] additive latency note: all other bit comb inations are illegal. 000 b al , 0 001 b al , 1 010 b al , 2 011 b al , 3 100 b al , 4 101 b al , 5 r tt 2,6 nominal termination resistance of odt 00 b rtt , (odt disabled) 01 b rtt , 75 ohm 10 b rtt , 150 ohm 11 b rtt , 50 ohm 2) dic 1 off-chip driver impedance control 0 b dic , full (driver size = 100%) 1 b dic , reduced dll 0 dll enable 0 b dll , enable 1 b dll , disable 1) w = write only register bits 2) optional for ddr2-400/533 & 667 table 11 extended mode register definition (ba[2:0] = 001b) field bits type 1) description
internet data sheet 19 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 12 emrs(2) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 w bank address[2] note: ba2 is not available on 256mbit and 512mbit components 0 b ba2 , bank address ba [15:14] w bank adress[15:14] 00 b ba , mrs 01 b ba , emrs(1) 10 b ba , emrs(2) 11 b ba , emrs(3): reserved a [13:8] w address bus[13:8] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a[13:8] , address bits a7 w address bus[7], adapted self refresh rate for tcase > 85 c 0 b a7 , disable 1 b a7 , enable 2) 2) when dram is operated at 85 c t case 95 c the extended self refresh rate must be enabled by setting bit a7 to "1" before the self refresh mode can be entered. a [6:4] w address bus[6:4] 0 b a[6:4] , address bits a3 w address bus[3], duty cycle correction (dcc) 0 b a[3] , dcc disabled 1 b a[3] , dcc enabled partial self refresh for 4 banks a [2:0] w address bus[2:0], partial array self refresh for 4 banks 3) 000 b pasr0 , full array 001 b pasr1 , half array (ba[1:0]=00, 01) 010 b pasr2 , quarter array (ba[1:0]=00) 011 b pasr3 , not defined 100 b pasr4 , 3/4 array (ba[1:0]=01, 10, 11) 101 b pasr5 , half array (ba[1:0]=10, 11) 110 b pasr6 , quarter array (ba[1:0]=11) 111 b pasr7 , not defined 3) if pasr (partial array self refresh) is enabled, data locate d in areas of the array beyond the specified location will be los t if self refresh is entered. data integrity will be maintained if t ref conditions are met and no self refresh command is issued 03%7 %$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu 65) '&& 3$65
internet data sheet 20 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 13 emr(3) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 reg.addr bank address[2] note: ba2 is not available on 256mbit and 512mbit components 0 b ba2 , bank address ba1 15 bank adress[1] 1 b ba1 , bank address ba0 14 bank adress[0] 1 b ba0 , bank address a[13:0]w address bus[13:0] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a[13:0] , address bits - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! r e g a d d r
internet data sheet 21 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram odt truth tables the odt truth table shows which of the input pins are terminated depending on the state of address bit a10 and a11 in the emrs(1) for all three device organisations ( 4, 8 and 16). to activate termination of any of these pins, th e odt function has to be enabled in the emrs(1) by address bits a6 and a2. note: x = don?t care; 0 = bit se t to low; 1 = bit set to high table 14 odt truth table input pin emrs(1) address bit a10 emrs(1) address bit a11 x4 components dq[3:0] x dqs x dqs 0x dm x x8 components dq[7:0] x dqs x dqs 0x rdqs x 1 rdqs 01 dm x 0 x16 components dq[7:0] x dq[15:8] x ldqs x ldqs 0x udqs x udqs 0x ldm x udm x
internet data sheet 22 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram notes 1. page size and length is a function of i/o organization: 128mb x 4 organization (ca[ 9:0], ca11); page size = 1 kbyte; page length = 2048 64mb x 8 organization (ca[9:0]); page size = 1 kbyte; page length = 1024 32mb x 16 organization (ca[9:0]); page size = 2 kbyte; page length = 1024 2. order of burst access for sequential addressing is ?nibble-based? and therefore different from sdr or ddr components table 15 burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
internet data sheet 23 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 4 truth tables table 16 command truth table function cke cs ras cas we ba0 ba1 a[13:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the stat es described in this table. the odt functi on is not available during self refresh. 2) ?x? means ?h or l (but a defined logic level)?. 3) operation that is not specified is ill egal and after such an event, in order to guarantee proper operat ion, the dram must be powered down and then restarted through the specified initialization sequence before no rmal operation can continue. previous cycle current cycle (extended) mode register set h h l l l l ba op code 4)5) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 5) bank addresses ba[1:0] determine which bank is to be ope rated upon. for (e)mrs ba[1:0] selects an (extended) mode register. auto-refresh h h l l l h x x x x ? self-refresh entry h l l l l h x x x x 6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x ? precharge all banks h h l l h l x x h x ? bank activate h h l l h h ba row address ? write h h l h l l ba column l column 8) 8) burst reads or writes at bl = 4 cannot be terminated. write with auto- precharge h h l h l l ba column h column ? read h h l h l h ba column l column ? read with auto- precharge h h l h l h ba column h column ? no operation h x l h h h x x x x ? device deselect h x h x x x x x x x power down entry h l h x x x x x x x 9) 9) the power down mode does not perform any refresh operations. lh h h power down exit l h h x x x x x x x ? lh h h
internet data sheet 24 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 17 clock enable (cke) truth table for synchronous transitions current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2)3) ras, cas, we, cs 2) command (n) is the command registered at clock edge n, and action (n) is a result of command (n) 3) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. action (n) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is ill egal and after such an event, in order to guarantee proper operat ion, the dram must be powered down and then restarted through the specified initialization sequence before no rmal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; cke (n-1) was the stat e of cke at the previous clock edge. current cycle (n) power-down l l x maintain power-down 7)8) 7) the power-down mode does not perform any refresh operations . the duration of power-down mode is therefor limited by the refresh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if t he odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 9)10)11) 9) all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) valid commands for po wer-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be registered on three consec utive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid leve l during the time period of t is + 2 t cke + t ih . self refresh l l x main tain self refresh 12) 12) v ref must be maintained during self refresh operation. l h deselect or nop self refresh exit 13)14) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refr esh exit are nop and deselct only. bank(s) active h l deselect or nop active power-down entry 15) 15) power-down and self refresh can not be entered while read or write operations , (extended) mode register operations, precharge or refresh operations are in progress. all banks idle h l deselect or nop precharge power-down entry ? h l autorefresh self refresh entry 16) 16) self refresh mode can only be enter ed from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. table 18 data mask (dm) truth table name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x ?
internet data sheet 25 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 5 electrical characteristics 5.1 absolute maximum ratings attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values maycause irreversible damage to the integrated circuit. table 19 absolute maximum ratings symbol parameter rating unit note v dd voltage on v dd pin relative to v ss ?1.0 to +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500mv; vref may be equal to or less than 300mv. v ddq voltage on v ddq pin relative to v ss ?0.5 to +2.3 v ? v ddl voltage on vddl pin relative to v ss ?0.5 to +2.3 v ? v in , v out voltage on any pin relative to v ss ?0.5 to +2.3 v ? t stg storage temperature ?55 to +100 c 2) 2) storage temperature is the case surface te mperature on the center/top side of the dram. table 20 dram component operating temperature range symbol parameter rating unit note t oper operating temperature 0 to 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dr am specification will be s upported. during operation, the dram case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) when operating this product in the 85 c to 95 c t case temperature range, the high temp erature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high tem perature self refresh is enab led there is an increase of i dd6 by approximately 50%
internet data sheet 26 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 5.2 dc characteristics table 21 recommended dc operating conditions (sstl_18) symbol parameter rating unit note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v ? v ddq supply voltage for output 1.7 1.8 1.9 v ? v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noise margin in the system. typicall y the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal terminatio n resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . table 22 odt dc electrical characteristics parameter / cond ition symbol min. nom. max. unit note termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i(v ihac ) and i(v ilac ) respectively. rtt(eff) = (v ih(ac) ? v il(ac) ) /(i(v ihac ) ? i(v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 ? ? termination resistor impedance value for emrs(1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 ? ? deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage (v m ) at test pin (midpoint) with no load: delta v m = ((2 x v m /v ddq )?1)x100% table 23 input and output leakage currents symbol parameter / condition min. max. unit note i il input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v i ol output leakage current; 0 v < vout < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off
internet data sheet 27 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 5.3 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or fa lling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and char acterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. table 24 dc & ac logic input leve ls for ddr2-667 and ddr2-800 symbol parameter ddr2-667, ddr2-800 units min. max. v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.200 ? v v il(ac) ac input low ? v ref ? 0.200 v table 25 dc & ac logic input leve ls for ddr2-533 and ddr2-400 symbol parameter ddr2- 533, ddr2-400 units min. max. v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref - 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v v il(ac) ac input low ? v ref - 0.250 v table 26 single-ended ac input test conditions symbol condition value unit note v ref input reference voltage 0.5 x v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing.max input signal maximum peak to peak swing 1.0 v ? slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac).min to v ref for rising edges and the range from v ref to v il(ac).max for falling edges as shown in figure 4 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions.
internet data sheet 28 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram figure 4 single-ended ac input test conditions diagram figure 5 differential dc and ac input and output logic levels diagram table 27 differential dc and ac input and output logic levels symbol parameter min. max. unit note v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) 1) v in(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which diff erential input signals must cross. v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which diff erential input signals must cross. 03(7 'howd75 'howd7) 9 6:,1*0$; 9 ''4 9 ,+df plq 9 ,+gf plq 9 5() 9 ,/gf pd[ 9 ,/df pd[ 9 66 5lvlqj6ohz 9 ,+df plq9 5() 'howd75 9 5() 9 ,/df pd[ )doolqj6ohz 'howd7) # r o s s i n g 0 o i n t 6 $ $ 1 6 3 3 1 6 ) $ 6 ) 8 o r 6 / 8 6 4 2 6 # 0
internet data sheet 29 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 5.4 output buffer characteristics table 28 sstl_18 output dc current drive symbol parameter sstl_18 unit note i oh output minimum source dc current ?13.4 ma 1)2) 1) v ddq = 1.7 v; v out = 1.42 v. ( v out ? v ddq ) / i oh must be less than 21 ohm for values of v out between v ddq and v ddq ? 280 mv. 2) the values of i oh(dc) and i ol(dc) are based on the conditions given in and . they are used to test drive current capability to ensure v ih.min . plus a noise margin and v il.max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement. i ol output minimum sink dc current 13.4 ma 3) 3) v ddq = 1.7 v; v out = 280 mv. v out / i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. table 29 sstl_18 output ac test conditions symbol parameter sstl_18 unit note v oh minimum required output pull-up v tt + 0.603 v 1) 1) sstl_18 test load for v oh and v ol is different from the referenced load. the sstl_18 test load has a 20 ohm series resistor additionally to the 25 ohm termination resistor into v tt . the sstl_18 definition assumes that 335 mv must be developed across the effectively 25 ohm termination resistor (13.4 ma 25 ohm = 335 mv). with an additional series resistor of 20 ohm this translates into a mi nimum requirement of 603 mv swing relative to v tt , at the ouput device (13.4 ma 45 ohm = 603 mv). v ol maximum required output pull-down v tt ? 0.603 v ? v otr output timing measurement reference level 0.5 v ddq v? table 30 ocd default characteristics symbol description min. nominal max. unit note ? output impedance ? ohms 1)2) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) impedance measurement conditio n for output source dc current: v ddq = 1.7 v, v out = 1420 mv; ( v out ? v ddq ) / i oh must be less than 23.4 ohms for values of v out between v ddq and v ddq ? 280 mv. impedance measurement condition for ou tput sink dc current: v ddq = 1.7 v; v out = ?280 mv; v out / i ol must be less than 23.4 ohms for values of v out between 0 v and 280 mv. ? pull-up / pull down mismatch 0 ? 4 ohms 3) 3) mismatch is absolute value between pull-up and pull- down, both measured at same temperature and voltage. ? output impedance step size for ocd calibration 0 ? 1.5 ohms 4) 4) this represents the step size when the ocd is near 18 ohms at nominal co nditions across all process parameters and represents only the dram uncertainty. a 0 ohm value (no ca libration) can only be achieved if the ocd impedance is 18 0.75 ohms under nominal conditions. s out output slew rate 1.5 ? 5.0 v / ns 5)6)7) 5) the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is verified by design and c haracterization but not subject to production test. 6) timing skew due to dram output slew rate mis-match between dqs / dqs and associated dq?s is included in t dqsq and t qhs specification. 7) dram output slew rate specification applie s to 400, 533 and 667 mt/s speed bins.
internet data sheet 30 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 5.5 input / output capacitance table 31 input / output capacitance symbol parameter min. max. unit cck input capacitance, ck and ck 1.0 2.0 pf cdck input capacitance delta, ck and ck ?0.25 pf ci input capacitance, all other input-only pins 1.0 1.75 pf cdi input capacitance delta, a ll other input-only pins ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs , rdqs, rdqs 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs , rdqs, rdqs ?0.5 pf
internet data sheet 31 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 5.6 overshoot and unde rshoot specification figure 6 ac overshoot / undershoot diagram for address and control pins table 32 ac overshoot / undershoot specification for address and control pins parameter ddr2?400 ddr2?533 ddr2?667 ddr2?800 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 v maximum overshoot area above v dd 1.33 1.00 0.80 0.80 v.ns maximum undershoot area below v ss 1.33 1.00 0.80 0.80 v.ns table 33 ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter ddr2?400 ddr2?533 ddr2?667 ddr2?800 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 v maximum overshoot area above v ddq 0.38 0.28 0.23 0.23 v.ns maximum undershoot area below v ssq 0.38 0.28 0.23 0.23 v.ns 03(7 9rowv9 9 '' 9 66 0d[lpxp$psolwxgh 7lphqv 0d[lpxp$psolwxgh 2yhuvkrrw$uhd 8qghuvkrrw$uhd
internet data sheet 32 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram figure 7 ac overshoot / undershoot diagram for clock, data, strobe and mask pins 03(7 9rowv9 9 ''4 9 664 0d[lpxp$psolwxgh 7lphqv 0d[lpxp$psolwxgh 2yhuvkrrw$uhd 8qghuvkrrw$uhd
internet data sheet 33 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 6 specifications and conditions table 34 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , cke is high, cs is high between valid commands. address and control inputs are switching; databus in puts are switching. i dd0 1)2)3)4) 5)6) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , t rcd = t rcd(idd) , al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd1 precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ;other control and address inputs are stable; data bus inputs are floating . i dd2p precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching . i dd2n precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit). i dd3p(0) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to 1 (slow power-down exit); i dd3p(1) active standby current all banks open; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switch ing; data bus inputs are switching; i dd3n operating current burst read: all banks open; continuous bu rst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bu s inputs are switching. i dd5b distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and addre ss inputs are switching, data bus inputs are switching. i dd5d
internet data sheet 34 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 operating bank interleave read current 1. all banks interleaving reads, i out = 0 ma; bl = 4, cl = cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. 2. timing pattern: i dd7 7) ddr2-400-333: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d (11 clocks) ddr2-533-333: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d (15 clocks) ddr2-667-444: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d (19 clocks) ddr2-667-555: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d (20 clocks) ddr2-800-555: a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d(22 clocks) ddr2-800-666: a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d(23 clocks) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd : see table 35 6) timing parameter minimum and maximum values for i dd current measurements are defined in chapter 7.. 7) a = activate, ra = read wi th auto-precharge, d=deselect table 35 definition for i dd parameter description low defined as v in v il(ac).max high defined as v in v ih(ac).min stable defined as inputs are stable at a high or low level floating defined as inputs are v ref = v ddq / 2 switching defined as: inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for dq signals not including mask or strobes table 34 i dd measurement conditions parameter symbol note
internet data sheet 35 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 36 i dd specification for hyb18t512xxxbf ?2.5f ?2.5 ?3 ?3s ?3.7 ?5 unit note ddr2-800d ddr2-800e ddr2-667c d dr2-667d ddr2-533c ddr2-400b symbol max. max. max. max. max. max. i dd0 84 80 75 71 65 61 ma 4/ 8 105 100 95 90 80 75 ma 16 i dd1 1009590 85 7570 ma 4/ 8 120 115 105 100 90 83 ma 16 i dd2p 777 7 77 ma? i dd2n 51 51 45 45 38 34 ma ? i dd2q 45 45 40 40 35 32 ma ? i dd3p 39 39 33 33 28 24 ma 1) 1) mrs(12)=0 999 9 99 ma 2) 2) mrs(12)=1 i dd3n 60 60 50 50 43 39 ma ? i dd4r 155 155 130 130 110 95 ma 4/ 8 180 180 155 155 130 115 ma 16 i dd4w 155 155 130 130 110 95 ma 4/ 8 200 200 170 170 145 130 ma 16 i dd5b 145 145 140 140 130 125 ma ? i dd5d 999 9 99 ma 3) 3) 0 t case 85 c. i dd6 777 7 77 ma? i dd7 170 160 160 152 145 141 ma 4/ 8 265 255 252 240 230 220 ma 16
internet data sheet 36 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 7 timing characteristics this chapter contains speed grade definiti on, ac timing parameter and odt tables. 7.1 speed grade definitions all speed grades faster than ddr2-ddr400b co mply with ddr2-ddr400b timing specifications( t ck = 5ns with t ras = 40ns). list of speed grade definition tables: ? table 37 ?speed grade definition speed bins ddr2?800? on page 36 ? table 38 ?speed grade definition speed bins for ddr2?667? on page 37 ? table 39 ?speed grade definition speed bins for ddr2?533c? on page 37 ? table 40 ?speed grade definition speed bins for ddr2?400b? on page 38 table 37 speed grade definition speed bins ddr2?800 speed grade ddr2?800d ddr2?800e unit note ifx sort name ?2.5f ?2.5 cas-rcd-rp latencies 5?5?5 6?6?6 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 58 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential stro be mode and a slew rate of 1 v/ns in single ended mode. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the cross point when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 3.75 8 ns ? @ cl = 5 t ck 2.5 8 3 8 ns ? @ cl = 6 t ck 2.5 8 2.5 8 ns ? row active time t ras 45 70000 45 70000 ns 5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57.5 ? 60 ? ns ? ras-cas-delay t rcd 12.5 ? 15 ? ns ? row precharge time t rp 12.5 ? 15 ? ns ?
internet data sheet 37 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 38 speed grade definition speed bins for ddr2?667 speed grade ddr2?667 ddr2?667 unit note ifx sort name ?3 ?3s cas-rcd-rp latencies 4?4?4 5?5?5 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 383.758ns? @ cl = 5 t ck 3838ns? row active time t ras 45 70000 45 70000 ns 5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57 ? 60 ? ns ? ras-cas-delay t rcd 12 ? 15 ? ns ? row precharge time t rp 12 ? 15 ? ns ? table 39 speed grade definition speed bins for ddr2?533c speed grade ddr2?533 unit note ifx sort name ?3.7 cas-rcd-rp latencies 4?4?4 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the cross point when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns ? @ cl = 5 t ck 3.75 8 ns ? row active time t ras 45 70000 ns 5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns ? ras-cas-delay t rcd 15 ? ns ? row precharge time t rp 15 ? ns ?
internet data sheet 38 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 40 speed grade definition speed bins for ddr2?400b speed grade ddr2?400 unit note ifx sort name ?5 cas-rcd-rp latencies 3?3?3 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 58 ns? @ cl = 5 t ck 58 ns? row active time t ras 40 70000 ns 5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 55 ? ns ? ras-cas-delay t rcd 15 ? ns ? row precharge time t rp 15 ? ns ?
internet data sheet 39 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 7.2 ac timing parameters list of timing parameters tables. ? table 41 ?timing parameter by speed grade - ddr2?800? on page 39 ? table 42 ?timing parameter by speed grade - ddr2?667? on page 41 ? table 43 ?timing parameter by speed grade - ddr2-533? on page 44 ? table 44 ?timing parameter by speed grade - ddr2-400? on page 47 table 41 timing parameter by speed grade - ddr2?800 parameter symbol ddr2?800 unit note 1)2)3)4)5) 6) min. max. dq output access time from ck / ck t ac ?400 +400 ps ? cas a to cas b command period t ccd 2? t ck ? ck, ck high-level width t ch 0.45 0.55 t ck ? cke minimum high and low pulse width t cke 3? t ck ? ck, ck low-level width t cl 0.45 0.55 t ck ? auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh (base) 125 ?? ps ? dq and dm input hold time (single ended data strobe) t dh1 (base) ?? ? ps ? dq and dm input pulse width (each input) t dipw 0.35 ? t ck ? dqs output access time from ck / ck t dqsck ?350 + 350 ps ? dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck ? dqs-dq skew (for dq s & associated dq signals) t dqsq ? 200 ps 9) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck ? dq and dm input setu p time (differential data strobe) t ds (base) 50 ? ps ? dq and dm input setup time (single ended data strobe) t ds1 (base) ?? ? ps ? dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck ? dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck ? clock half period t hp min. ( t cl, t ch )? 10) data-out high-impedance time from ck / ck t hz ? t ac.max ps 11) address and control input hold time t ih (base) 250 ? ps ? address and control input pulse width (each input) t ipw 0.6 ? t ck ?
internet data sheet 40 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram address and control input setup time t is (base) 175 ? ps ? dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps ? dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps ? mode register set command cycle time t mrd 2? t ck ? ocd drive mode output delay t oit 012ns? data output hold time from dqs t qh t hp ? t qhs ??? data hold skew factor t qhs ? 300 ps ? average periodic refresh interval t refi ?7.8 s 12)13) ?3.9 s 14) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? ns 15) precharge-all (4 banks) command period t rp t rp ?ns 16) read preamble t rpre 0.9 1.1 t ck ? read postamble t rpst 0.40 0.60 t ck ? active bank a to active bank b command period t rrd 7.5 ? ns 17) 10 ? ns ? internal read to precharge command delay t rtp 7.5 ? ns ? write preamble t wpre 0.35 x t ck ? t ck ? write postamble t wpst 0.40 0.60 t ck 18) write recovery time for write without auto- precharge t wr 15 ? ns ? write recovery time for write with auto- precharge wr t wr / t ck ? t ck 19) internal write to read command delay t wtr 7.5 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 8 ? al ? t ck ? exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck ? exit self-refresh to non-read command t xsnr t rfc +10 ? ns ? exit self-refresh to read command t xsrd 200 ? t ck ? 1) v ddq = 1.8v 0.1v; v dd = 1.8v 0.1 v. see notes 2) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . table 41 timing parameter by speed grade - ddr2?800 (cont?d) parameter symbol ddr2?800 unit note 1)2)3)4)5) 6) min. max.
internet data sheet 41 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr para meter stored in the mr. 8) the clock frequency is allowed to change during self-refr esh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required. 9) consists of data pin skew and output patt ern effects, and p-channel to n-channel vari ation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 10) min ( t cl , t ch ) refers to the smaller of the actual clock low time and th e actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 11) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage le vel, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid data transitions.these parameters ar e verified by design and characterizati on, but not subject to production test. 12) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 13) 0 c t case 85 c 14) 85 c < t case 95 c 15) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 16) t rp (a) for a precharge-all command for an 8 bank device is equal to t rp + 1 t ck , where t rp are the values for a single bank precharge. 17) the t rrd timing parameter depends on the page size of the dram organization. see chapter 1 18) the maximum limit for the t wpst parameter is not a device limit. the device oper ates with a greater value for this parameter, but system performance (bus turn around) degrades accordingly. 19) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active power-down modes for ad ditional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. table 42 timing parameter by speed grade - ddr2?667 parameter symbol ddr2?667 unit note 1)2)3)4)5) 6) min. max. dq output access time from ck / ck t ac ?450 + 450 ps ? cas a to cas b command period t ccd 2? t ck ? ck, ck high-level width t ch 0.45 0.55 t ck ? cke minimum high and low pulse width t cke 3? t ck ? ck, ck low-level width t cl 0.45 0.55 t ck ? auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?ns 8) dq and dm input hold time (differential data strobe) t dh (base) 175 ?? ps ? dq and dm input hold time (single ended data strobe) t dh1 (base) ?? ? ps ? dq and dm input pulse width (each input) t dipw 0.35 ? t ck ? dqs output access time from ck / ck t dqsck ?400 + 400 ps ? dqs input low (high) pu lse width (write cycle) t dqsl,h 0.35 ? t ck ?
internet data sheet 42 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram dqs-dq skew (for dq s & associated dq signals) t dqsq ?240ps 9) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck ? dq and dm input setup ti me (differential data strobe) t ds (base) 100 ? ps ? dq and dm input setup time (single ended data strobe) t ds1 (base) ?? ? ps ? dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck ? dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck ? clock half period t hp min. ( t cl, t ch )? 10) data-out high-impedance time from ck / ck t hz ? t ac.max ps 11) address and control input hold time t ih (base) 275 ? ps ? address and control input pulse width (each input) t ipw 0.6 ? t ck ? address and control input setup time t is (base) 200 ? ps ? dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps ? dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps ? mode register set command cycle time t mrd 2? t ck ? ocd drive mode output delay t oit 012ns? data output hold time from dqs t qh t hpq ? t qhs ??? data hold skew factor t qhs ?340ps? average periodic refresh interval t refi ?7.8 s 12)13) ?3.9 s 14) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? ns 15) precharge-all (4 banks) command period t rp t rp ?ns 16) read preamble t rpre 0.9 1.1 t ck ? read postamble t rpst 0.40 0.60 t ck ? active bank a to active bank b command period t rrd 7.5 ? ns 17) 10 ? ns ? internal read to precharge command delay t rtp 7.5 ? ns ? write preamble t wpre 0.35 x t ck ? t ck ? write postamble t wpst 0.40 0.60 t ck 18) write recovery time for write without auto- precharge t wr 15 ? ns ? write recovery time for write with auto- precharge wr t wr / t ck ? t ck 19) internal write to read command delay t wtr 7.5 ? ns 20) table 42 timing parameter by speed grade - ddr2?667 (cont?d) parameter symbol ddr2?667 unit note 1)2)3)4)5) 6) min. max.
internet data sheet 43 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? t ck ? exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck ? exit self-refresh to non-read command t xsnr t rfc +10 ? ns ? exit self-refresh to read command t xsrd 200 ? t ck ? 1) v ddq = 1.8v 0.1v; v dd = 1.8v 0.1 v. see notes 2) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr para meter stored in the mr. 8) the clock frequency is allowed to change during self-refr esh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required. 9) consists of data pin skew and output pattern effe cts, and p-channel to n-channel variati on of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 10) min ( t cl , t ch ) refers to the smaller of the actual cl ock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 11) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific volt age level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid data transitions.these parameters ar e verified by design and characterizati on, but not subject to production test. 12) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 13) 0 c t case 85 c 14) 85 c < t case 95 c 15) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 16) t rp (a) for a precharge-all command for an 8 bank device is equal to t rp + 1 t ck , where t rp are the values for a single bank precharge. 17) the t rrd timing parameter depends on the page size of the dram organization. see chapter 1 18) the maximum limit for the t wpst parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turn around) degrades accordingly. 19) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active power-down modes for additional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. table 42 timing parameter by speed grade - ddr2?667 (cont?d) parameter symbol ddr2?667 unit note 1)2)3)4)5) 6) min. max.
internet data sheet 44 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 43 timing parameter by speed grade - ddr2-533 parameter symbol ddr2?533 unit note 1)2)3)4) 5)6) min. max. dq output access time from ck / ck t ac ?500 +500 ps ? cas a to cas b command period t ccd 2? t ck ? ck, ck high-level width t ch 0.45 0.55 t ck ? cke minimum high and low pulse width t cke 3? t ck ? ck, ck low-level width t cl 0.45 0.55 t ck ? auto-precharge wr ite recovery + precharge time t dal wr + t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh (base) 225 ?? ps ? dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps ? dq and dm input pulse width (each input) t dipw 0.35 ? t ck ? dqs output access time from ck / ck t dqsck ?450 + 450 ps ? dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck ? dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps 9) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck ? dq and dm input setu p time (differential data strobe) t ds (base) 100 ? ps ? dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps ? dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck ? dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck ? clock half period t hp min. ( t cl, t ch )? 10) data-out high-impedance time from ck / ck t hz ? t ac.max ps 11) address and control input hold time t ih (base) 375 ? ps ? address and control input pulse width (each input) t ipw 0.6 ? t ck ? address and control input setup time t is (base) 250 ? ps ? dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps ? dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps ? mode register set command cycle time t mrd 2? t ck ? ocd drive mode output delay t oit 012ns? data output hold time from dqs t qh t hp ? t qhs ???
internet data sheet 45 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram data hold skew factor t qhs ? 400 ps ? average periodic refresh interval t refi ?7.8 s 12)13) ?3.9 s 14) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? ns 15) precharge-all (4 banks) command period t rp t rp ?ns 16) read preamble t rpre 0.9 1.1 t ck ? read postamble t rpst 0.40 0.60 t ck ? active bank a to active bank b command period t rrd 7.5 ? ns 17) 10 ? ns ? internal read to precharge command delay t rtp 7.5 ? ns ? write preamble t wpre 0.25 x t ck ? t ck ? write postamble t wpst 0.40 0.60 t ck 18) write recovery time for write without auto- precharge t wr 15 ? ns ? write recovery time for write with auto- precharge wr t wr / t ck ? t ck 19) internal write to read command delay t wtr 7.5 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck ? exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck ? exit self-refresh to non-read command t xsnr t rfc +10 ? ns ? exit self-refresh to read command t xsrd 200 ? t ck ? 1) v ddq = 1.8v 0.1v; v dd = 1.8v 0.1 v. see notes 2) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr para meter stored in the mr. 8) the clock frequency is allowed to change during self-refr esh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required. 9) consists of data pin skew and output patter n effects, and p-channel to n-channel vari ation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 10) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). table 43 timing parameter by speed grade - ddr2-533 (cont?d) parameter symbol ddr2?533 unit note 1)2)3)4) 5)6) min. max.
internet data sheet 46 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 11) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltag e level, which specify w hen the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid data transitions.these parameters ar e verified by design and characterizati on, but not subject to production test. 12) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 13) 0 c t case 85 c 14) 85 c < t case 95 c 15) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 16) t rp (a) for a precharge-all command for an 8 bank device is equal to t rp + 1 t ck , where t rp are the values for a single bank precharge. 17) the t rrd timing parameter depends on the page size of the dram organization. see chapter 1 18) the maximum limit for the t wpst parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turn around) degrades accordingly. 19) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active power-down modes for a dditional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied.
internet data sheet 47 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 44 timing parameter by speed grade - ddr2-400 parameter symbol ddr2?400 unit note 1)2)3)4)5) 6) min. max. dq output access time from ck / ck t ac ?600 +600 ps ? cas a to cas b command period t ccd 2? t ck ? ck, ck high-level width t ch 0.45 0.55 t ck ? cke minimum high and low pulse width t cke 3? t ck ? ck, ck low-level width t cl 0.45 0.55 t ck ? auto-precharge wr ite recovery + precharge time t dal wr + t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh (base) 275 ?? ps ? dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps ? dq and dm input pulse width (each input) t dipw 0.35 ? t ck ? dqs output access time from ck / ck t dqsck ?500 + 500 ps ? dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck ? dqs-dq skew (for dqs & associated dq signals) t dqsq ? 350 ps 9) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck ? dq and dm input setu p time (differential data strobe) t ds (base) 150 ? ps ? dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps ? dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck ? dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch )? 10) data-out high-impedance time from ck / ck t hz ? t ac.max ps 11) address and control input hold time t ih (base) 475 ? ps ? address and control input pulse width (each input) t ipw 0.6 ? t ck ? address and control input setup time t is (base) 350 ? ps ? dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps ? dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps ? mode register set command cycle time t mrd 2? t ck ? ocd drive mode output delay t oit 012ns? data output hold time from dqs t qh t hp ? t qhs ???
internet data sheet 48 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram data hold skew factor t qhs ? 450 ps ? average periodic refresh interval t refi ?7.8 s 12)13) ?3.9 s 14) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? ns 15) precharge-all (4 banks) command period t rp t rp ?ns 16) read preamble t rpre 0.9 1.1 t ck ? read postamble t rpst 0.40 0.60 t ck ? active bank a to active bank b command period t rrd 7.5 ? ns 17) 10 ? ns ? internal read to precharge command delay t rtp 7.5 ? ns ? write preamble t wpre 0.25 x t ck ? t ck ? write postamble t wpst 0.40 0.60 t ck 18) write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck ? t ck 19) internal write to read command delay t wtr 10 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck ? exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck ? exit self-refresh to non-read command t xsnr t rfc +10 ? ns ? exit self-refresh to read command t xsrd 200 ? t ck ? 1) v ddq = 1.8v 0.1v; v dd = 1.8v 0.1 v. see notes 2) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) for each of the terms, if not already an in teger, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr para meter stored in the mr. 8) the clock frequency is allowed to change during self-refr esh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required. 9) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 10) min ( t cl , t ch ) refers to the smaller of the actual clock low time and th e actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). table 44 timing parameter by speed grade - ddr2-400 parameter symbol ddr2?400 unit note 1)2)3)4)5) 6) min. max.
internet data sheet 49 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 11) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid data transitions.these parameters ar e verified by design and characterizati on, but not subject to production test. 12) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 13) 0 c t case 85 c 14) 85 c < t case 95 c 15) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 16) t rp (a) for a precharge-all command fo r an 8 bank device is equal to t rp + 1 t ck , where t rp are the values for a single bank precharge. 17) the t rrd timing parameter depends on the page size of the dram organization. see chapter 1 18) the maximum limit for the t wpst parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turn around) degrades accordingly. 19) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active power-down modes for a dditional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied.
internet data sheet 50 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 7.3 odt ac electrical characteristics table 45 odt ac electrical characteristics and operating conditions for ddr2-667 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck ? t aon odt turn-on t ac.min t ac.max +0.7ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max +1 ns ns ? t aofd odt turn-off delay 2.5 2.5 t ck ? t aof odt turn-off t ac.min t ac.max +0.6ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns ? t anpd odt to power down mo de entry latency 3 ? t ck ? t axpd odt power down exit latency 8 ? t ck ? table 46 odt ac electrical char acteristics and operating condit ions for ddr2-533 and ddr2-400 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck ? t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns ? t aofd odt turn-off delay 2.5 2.5 t ck ? t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns ? t anpd odt to power down mo de entry latency 3 ? t ck ? t axpd odt power down exit latency 8 ? t ck ?
internet data sheet 51 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 8 package dimensions figure 8 package pinout pg-tfbga-60 x " x ! - ) . - ! 8 ? ? x ? ? " - - ! # 3 % ! 4 ) . ' 0 , ! . % # # $ u m m y p a d s w i t h o u t b a l l 0 a c k a g e o r i e n t a t i o n m a r k ! - i d d l e o f p a c k a g e s e d g e s - ! 8 - ! 8 # " a d u n i t m a r k i n g " 5 - $ i e s o r t f i d u c i a l
internet data sheet 52 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram figure 9 package outline p-tfbga-84 x ! " ? ? ? - ? x - # ! " - ! 8 - ) . # 3 % ! 4 ) . ' 0 , ! . % - i d d l e o f p a c k a g e s e d g e s " a d u n i t m a r k i n g " 5 - 0 a c k a g e o r i e n t a t i o n m a r k ! $ u m m y p a d s w i t h o u t b a l l $ i e s o r t f i d u c i a l x - ! 8 # # - ! 8
internet data sheet 53 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 9 product nomenclature for reference the qimonda sdram component no menclature is enclosed in this chapter. table 47 nomenclature fields and examples example for field number 1 234567891011 ddr2 dram hyb 18 t 512 16 0 a c ?3.7 table 48 ddr2 memory components field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 m 512 512 m 1g 1 gb 5+6 number of i/os 40 4 80 8 160 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?3 ddr2?667 4?4?4 ?3s ddr2?667 5?5?5 ?3.7 ddr2?533 4?4?4 ?5 ddr2?400 3?3?3 11 n/a for components
internet data sheet 54 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram figure 1 pin configuration for 4 components, pg-tfbga-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2 pin configuration for 8 components, pg-tfbga-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3 pin configuration for 16 components, pg-tfbga-84-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4 single-ended ac input test conditio ns diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5 differential dc and ac input and output logic levels diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6 ac overshoot / undershoot diagram for address and co ntrol pins . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7 ac overshoot / undershoot diagr am for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . 32 figure 8 package pinout pg-tfbga-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 9 package outline p-tfbga-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 list of figures
internet data sheet 55 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram table 1 performance for ddr2?800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 performance for ddr2?667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3 performance for ddr2?533c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 4 performance for ddr2?400b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 5 ordering information for rohs compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 6 pin configuration of ddr2 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 7 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9 512-mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10 mode register definition (ba[2:0] = 000b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11 extended mode register definition (ba[2:0] = 001b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 table 12 emrs(2) programming extended mode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . 19 table 13 emr(3) programming extended mode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . . 20 table 14 odt truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 15 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 16 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17 clock enable (cke) truth table for synchronous transiti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20 dram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 21 recommended dc operating conditions (sstl_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 22 odt dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 23 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 24 dc & ac logic input levels for ddr2-667 and ddr2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 25 dc & ac logic input levels for ddr2-533 and ddr2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 26 single-ended ac input test conditio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 27 differential dc and ac input and output logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 28 sstl_18 output dc current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 29 sstl_18 output ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 30 ocd default characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 31 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 32 ac overshoot / undershoot specification for address and control pins . . . . . . . . . . . . . . . . . . . 31 table 33 ac overshoot / undershoot spec ification for clock, data, strobe and mask pins . . . . . . . . . . . . 31 table 34 i dd measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 35 definition for i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 36 i dd specification for hyb18t512xxxbf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 37 speed grade definition speed bins ddr2?800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 38 speed grade definition speed bins for ddr2?667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 39 speed grade definition speed bins for ddr2?533c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 40 speed grade definition speed bins for ddr2?400b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 41 timing parameter by speed grade - ddr2?800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 42 timing parameter by speed grade - ddr2?667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 43 timing parameter by speed grade - ddr2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 44 timing parameter by speed grade - ddr2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 table 45 odt ac electrical characteristics and operating conditions for ddr2-667 . . . . . . . . . . . . . . . . 50 table 46 odt ac electrical charac teristics and operating conditions for ddr2-533 and ddr2-400 . . . . 50 table 47 nomenclature fields and examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 48 ddr2 memory components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 list of tables
internet data sheet 56 rev. 1.05, 2007-01 03292006-ybym-wg0z hyb18t512xxxbf?[2.5?5] 512-mbit double-data -rate-two sdram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 512 mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 product nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table of contents
edition 2007-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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